The present invention relates in general to high speed integrated circuitry, and in particular to methods and circuitry for implementing high gain driver amplifiers having very large bandwidth of the type used in optical communication systems.
The coming of the modern information age has brought about phenomenal growth in demand for telecommunications-based services and products, driven primarily by the Internet. As the burgeoning expansion of the Internet continues along an unprecedented and unpredictable path, many new applications are foreseen and expected. These applications are placing increasing demands for ultra-high speed circuit solutions that maximize integration while minimizing power consumption among other requirements. In parallel, driven by the explosive growth in bandwidth requirements of multimedia applications, various ultra-high bit rate transmission techniques have been developed. Fiber-optic communications system speeds have increased from asynchronous-transfer-mode (ATM) rates of 155 Mb/s and synchronous optical network (SONET) rates of 622 Mb/s to the optical carrier (OC) standard of OC-192 at 10 Gb/s and OC-768 at 40 Gb/s.
Recent advances in optical and semiconductor processing technologies are enabling 40 Gb/s systems to move from research laboratories to production ready systems that can be manufactured in large volumes. However, the design of various functional blocks, especially at the interface with the fiber, remains a challenging task. For example, one of the most critical circuits in an optical transmitter is the amplifier in the optical modulator that drives the fiber. At the 40 Gb/s rate, the amplifier must exhibit very large bandwidth. It is also required to drive a relatively large signal (e.g.,  greater than 7Vpp). The large bandwidth required smaller and faster transistors while the higher voltage operation requires the opposite. The driver amplifier is also required to perform a limiting function to achieve stable eye diagram at its output. These various and competing requirements create a set of tradeoffs that make the task of designing the amplifier a particularly difficult one.
Current approaches to designing the driver amplifier are based on a distributed amplifier architecture. This type of an amplifier connects a number of parallel amplifier cells that are typically made up of a single transistor or a cascoded pair of transistors. The limiting function is achieved by making the amplifier work in deep saturation. The power compression in this design, however, causes about 3-4 dB of gain loss, requiring more cells to achieve the desired overall gain or several cascaded devices. A larger number of amplifiers cells, however, results in lower bandwidth and increased power consumption. An alternative approach separates the limiting function from the amplifier by using a limiter circuit that drives one or more distributed amplifiers such that the amplifier need not operate in saturation region. There are drawbacks to this approach as well. At 40 Gb/s, most of the circuitry is implemented in a single-ended architecture and as such, the addition of a single-ended limiter reduces the overall achievable gain, while the power levels remain as another constraint.
An improvement has been offered by an implementation that combines two distributed amplifiers in parallel to obtain an additional 3 dB of voltage gain and a higher output voltage. The combined amplifier thus includes two input gate lines and a common high current drain line. To drive the two input gate lines, a divider (or splitter) preamplifier is used which receives the single-ended output of the limiter and produces two output signals that drive the two input gate lines of the final amplifier which is commonly referred to as the combiner amplifier. While this approach has provided improvements in the power versus bandwidth tradeoff, it has added more circuitry and still requires a single-ended limiter. Additionally, this solution requires a large DC level shift (from about 8V down to near 0V) between the output of the divider preamplifier and the combiner amplifier. This level shift typically requires large passive elements such as resistors or capacitors that are too large to be integrated on the same chip as the amplifier and add to the power consumption of the device.
There is therefore a need for improved methods and circuitry for implementing high gain wideband amplifiers.
The present invention provides methods and circuitry for implementing monolithic high gain wideband amplifiers. Broadly, the invention implements an amplifier with a limiter that also performs the divider function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive the two gate input lines of a combiner distributed amplifier. The resulting amplifier essentially eliminates the divider distributed preamplifier of the prior art while achieving the desired bandwidth, gain and power. The limiter/divider of the invention also reduces the level shifting task to small enough levels to eliminate the need for large capacitors or resistors allowing a higher level of integration.
Accordingly, in one embodiment, the present invention provides an amplifier circuit including a limiter preamplifier having a differential amplifier coupled to receive a differential signal at its inputs and configured to generate a differential output signal made up of a first output signal and a second output signal, and an output stage having a first differential output amplifier coupled to the first output signal and a second differential output amplifier coupled to the second output signal; and a combiner distributed amplifier having a first input coupled to an output of the first differential output amplifier, and a second input coupled to an output of the second differential output amplifier, wherein the output of the first differential output amplifier and the output of the second differential output amplifier are of the same phase.
In another embodiment, the present invention provides a method of amplifying a high frequency signal including receiving a differential signal at differential inputs of a limiter circuit; performing a limiting function on the differential signal; using the limiter circuit to generate a pair of in-phase output signals; and applying, respectively, the pair of in-phase output signals to a pair of input terminals of a combiner distributed amplifier.
In yet another embodiment, the present invention provides a limiter amplifier having a differential amplifier cell coupled to receive a differential signal at its inputs and configured to generate a differential output signal made up of a first signal and a second signal; and an output stage having a first differential output amplifier coupled to the first signal and a second differential output amplifier coupled to the second signal, wherein the first differential output amplifier is configured to generate a first single-ended output signal and the second differential output amplifier is configured to generate a second single-ended output signal that is in phase with the first single-ended output signal.
The following detailed description and the accompanying drawings will provide a better understanding of the nature and advantages of the driver amplifier of the present invention.